One or more aspects of the invention relate generally to analyzing design problems of electronic chips, and in particular, to analyzing a timing endpoint report for a design of an electronic circuit.
Advancing semiconductor manufacturing technology allows squeezing more and more functionality, and thus, transistors on a single semiconductor chip. By increasing the complexity within a chip design, dependencies between different functional points, size and placement of individual devices, as well as physical/geometrical paths between logically dependent functions also increase. Additionally, the operational speed is ever increasing using higher and higher clock rates. Timing issues arise even when using synthesis tools for selected functions because these synthesis tools may not be perfect. That is, several timing problems remain in synthesized circuits. Thus, a manual analysis and repair of the circuit design may be required. One solution to address this problem is a usage of endpoint reports as a result of an automatic analysis of a designed circuit. Such endpoint reports look for critical signal paths in the design but which do not directly reveal what circuit design flaws need to be improved. In order to find these circuit design flaws in an endpoint report, a series of manual steps are currently required to be performed by a system designer. The system designer needs to bring in his/her experience and time to find the circuit design flaws.